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The SP7021 support 8 sets PWM module output. The PWM module can base on system clock or a specific 54MHz frequency to produce PWM signals. The PWM frequency and duty can be set by registers. The PWM control registers locate in RGST Table Group 244 which memory map to address 0x9C007A00~0x9C007A7F.
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| Field Name | Bit | Access | Description |
| reserved0 | 15:12 | RO | |
| PWM DD3 SYNC OFF | 11 | RW | PWM duty divisor count 3 sync off PWM phase do sync format timing 0: Turn ON 1: Turn OFF (default) |
| PWM DD2 SYNC OFF | 10 | RW | PWM duty divisor count 2 sync off PWM phase do sync format timing 0: Turn ON 1: Turn OFF (default) |
PWM DD1 SYNC OFF | 9 | RW | PWM duty divisor count 1 sync off |
PWM DD0 SYNC OFF | 8 | RW | PWM duty divisor count 0 sync off |
reserved1 | 7:5 | RO | |
PWM CLK54 ENreserved2 | 4RWPWM | cycle base on 54MHz | |
PWM CNT3 EN | 3 | RW | PWM DD3 count enable |
PWM CNT2 EN | 2 | RW | PWM DD2 count enable |
PWM CNT1 EN | 1 | RW | PWM DD1 count enable |
PWM CNT0 EN | 0 | RW | PWM DD0 count enable |
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