...
This is convenient for users to connect their own IP with AMBA bus interface to the Bus Bridge. At present,
the following specifications of Bus Bridge are provided for users, as shown in the table below:
Bus Bridge 模块 | 规格 | |||
axi_bus_m64s64_bridge | AXI Master | AXI Slave | ||
数据位宽 | 64bit | 数据位宽 | 64bit | |
地址位宽 | 32bit | 地址位宽 | 32bit | |
Burst传输 | 支持(最大16) | Burst传输 | 支持(最大16) | |
axi_bus_m32s32_bridge | AXI Master | AXI Slave | ||
数据位宽 | 32bit | 数据位宽 | 32bit | |
地址位宽 | 32bit | 地址位宽 | 32bit | |
Burst传输 | 支持(最大16) | Burst传输 | 支持(最大16) | |
axi_bus_m32_bridge | AXI Master |
| ||
数据位宽 | 32bit | |||
地址位宽 | 32bit | |||
Burst传输 | 支持(最大16) | |||
axi_bus_s32_bridge |
| AXI Slave | ||
数据位宽 | 32bit | |||
地址位宽 | 32bit | |||
Burst传输 | 支持(最大16) | |||
apb_bus_m32_bridge | APB Master |
| ||
数据位宽 | 32bit | |||
地址位宽 | 32bit | |||
Burst传输 | 无 | |||
5.4.3 Introduction to Bus Bridge module Memory Mapping
...
The address space of the Bus Bridge module is mapped to the corresponding 128MB address space of the system, as follows:
Device Name | CPU View Address | Size |
Bus Bridger | 0x7000_0000~0x77FF_FFFF (un-cacheable) | 128MB |
In this way, the register address in the user IP is used in this area. For example, the four registers in the IP core design practice of the seven-segment digital display controller introduced in the previous chapter, the corresponding definitions during system software development, refer to
...
- The blue above defines the starting address of the Bus Bridge Wrapper module; the red defines the 4 registers related to the digital control IP, and their addresses are as follows after the program is compiled
Nixie tube control IP register | Corresponding to the SP7021 system ARM CPU addressing space |
EX_CON | 0x70000000 |
EX_TO | 0x70000004 |
EX_BUFFER | 0x70000008 |
EX_STATE | 0x7000000c |
The interrupt numbers assigned by the SP7021 system are shown in the following table:
| Interrupt Number |
EXT0_INT | 29 |
EXT1_INT | 30 |
5.4.4 Bus Bridge function introduction
...
5.4.4.1. Bus Bridge Pin description
soc_top.v | Abbrev. | Description |
FPGA_PAD[0] | rxd[0] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[1] | rxd[2] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[2] | rxd[4] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[3] | rxd[6] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[4] | rxd[8] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[5] | rxd[10] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[6] | rxd[12] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[7] | rxd[14] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[8] |
rxvld |
SP7021 Chip to FPAG, to indicate RX channel data |
valid | ||
FPGA_PAD[9] | txclk | FPGA to SP7021 Chip TX channel clock |
FPGA_PAD[10] | txd[0] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[11] | txd[2] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[12] | txd[4] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[13] | txd[6] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[14] | txd[10] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[15] | txd[12] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[16] | txd[14] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[17] |
txvld | FPGA to SP7021 Chip, to indicate TX channel data |
valid | ||
FPGA_PAD[18] |
| SP7021 Chip to FPGA Reset |
FPGA_PAD[19] |
| FPGA to SP7021 Chip Interrupt |
FPGA_PAD[20] |
|
|
FPGA_PAD[21] |
|
|
FPGA_PAD[22] |
|
|
FPGA_PAD[23] |
| FPGA to SP7021 Chip Interrupt |
FPGA_PAD[24] |
txrdy | FPGA to SP7021 Chip |
,handshake with rxvld to implement RX channel data |
receive | ||
FPGA_PAD[25] | txd[15] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[26] | txd[13] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[27] | txd[11] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[28] | txd[9] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[29] | txd[8] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[30] | txd[7] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[31] | txd[5] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[32] | txd[3] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[33] | txd[1] | FPGA to SP7021 Chip TX channel data |
FPGA_PAD[34] |
rxrdy | SP7021 Chip to FPGA |
,handshake with txvld to implement TX channel data |
transmit | ||
FPGA_PAD[35] | rxclk | SP7021 Chip to FPGA RX channel clock |
FPGA_PAD[36] | rxd[15] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[37] | rxd[13] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[38] | rxd[11] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[39] | rxd[9] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[40] | rxd[7] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[41] | rxd[5] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[42] | rxd[3] | SP7021 Chip to FPGA RX channel data |
FPGA_PAD[43] | rxd[1] | SP7021 Chip to FPGA RX channel data |
Note: In order to facilitate users to develop and verify their own IP, the FPGA development environment provided in this experiment already contains the Bus Bridge module part, users only need to integrate their IP into the FPGA environment
...