17. SPI NOR

17.1 Introduction

This section describes the SPI_NOR Controller and its function. The SPI_NOR Controller is used to transmit or receive data with SPI_NOR device. The control registers locate at RGST Table Group 22&23 which memory map address are 0x9C000B00~0x9C000BFF. The SPINOR controller has below features.

  • Support 32-bit AXI master bus for transferring data between controller and dram for DMA mode
  • Exchange to 32-bit AXI Slave bus from 32-bit OCP bus
  • Support auto multi page read
  • Support auto multi page program
  • Support SPI_CLK is divided from CLK_SPI, and frequency division coefficient is 1/2, 1/4, 1/6, 1/8, 1/16, 1/24, 1/32


17.2 Function Diagram

A generalized function diagram of SPINOR is shown in Figure 17-1. SPI_NOR_BCHIF is revered for SPI_NOR Controller. BCH function is only useful for SPI_NAND controller.

Figure 17-1 SPI NOR Functional Blocks

  • SPI_NOR_REG: This block is used for register configure.
  • SPI_NOR_DMA: Support 32-bit AXI master bus to read/write data between controller and dram for DMA mode.
  • SPI_NOR_CON: This block is used for controlling the operation flow
  • SPI_NOR_OUT: SPI interface with external SPI device.
  • SPI_NOR _ASYNC: For async information between SPI_NOR_CON and SPI_NOR_OUT
  • SPI_NOR_AXI_S: Exchange to 32-bit AXI Slave bus from 32-bit OCP bus.
  • SPI_PROTECT: This block is used for protect the configuration regions of SPI_NOR flash size.


17.3 Data Control Timing

SPI_NOR Controller TX timing: The TX output start timing decides by spi_timing[0] which is bit0 of Group 22.1 spi_timing register. When spi_timing[0]=1 , TX will advance one system clock cycle to send data. Please refer to figure 17-2.

Figure 17-2 TX timing chart
SPI_NOR Controller RX timing: The RX timing can be fine tune by spi_timing[3:1] which is bit[3:1] of Group 22.1 spi_timing register.

  • Figure 17-3 RX timing chart


  • If the pad TX delay is t1,than from device to response data until SPI Controller receive data the delay is t2.
  • NEG_SAMPLE is spi_controller default sample point
  • As above figure,controller can't get correct data in the default sample point,user can fine tune spi_timing[3:1] to get correct read timing. For example, in figure 17-3 set spi_timing[3:1]=1 can get correct sample data.


17.4 SPI NOR Interrupts

The SPINOR interrupt events are connected to the same interrupt vector, please refer to figure 17-4. These events generate an interrupt if the corresponding "Mask Bit" isn't set. The mask control register is in Group 22.17. The interrupt status register is in Group 22.18. SPI_NOR controller interrupt is a level signal. It supports three kinds of interrupt status. If one interrupt mask enable, this interrupt will only update the status, the SPINOR_INT will not be set.

Figure 17-4 SPINOR Interrupt Tree
SPI interrupt status register (Group 22.18 spi_intr_sts) description.

  • PIO_DONE_INTR: When PIO mode transfer finished, spi_intr_sts[2] will be high. Software write 1 to clean this bit.
  • DMA_DONE_INTR: spi_intr_sts[1] indicate the current dma operation is done. Software can write 1 to clear this bit
  • BUF_DATA_ENOU_INTR: spi_intr_sts[0] indicate the number of data received from flash has reached the setting amount. Software can write 1 to clear this bit. The amount is set in spi_cfg0[21] which is bit 21 of Group 22.6 register. Set spi_cfg0[21]=1, the buffer size is 32byte. Set spi_cfg0[21]=0, the buffer size is 64byte.




17.5 Registers Map

17.5.1 Registers Memory Map

Address

Group No.

Register Name

Register Description

0x9C000B00

G22.0

Spi_Ctrl

SPI control Register

0x9C000B04

G22.1

Spi_timing

SPI timing Register

0x9C000B08

G22.2

Spi_page_addr

SPI Page Address Register

0x9C000B0C

G22.3

Spi_data

SPI Data Register

0x9C000B10

G22.4

Spi_status

SPI Status Register

0x9C000B14

G22.5

Spi_auto_cfg

SPI Auto Mode Configuration Register

0x9C000B18

G22.6

Spi_cfg0

SPI Configuration0 Register

0x9C000B1C

G22.7

Spi_cfg1

SPI Configuration1 Register

0x9C000B20

G22.8

Spi_cfg2

SPI Configuration2 Register

0x9C000B24

G22.9

Spi_data_64

SPI Data Buffer Register

0x9C000B28

G22.10

Spi_buf_addr

SPI Buffer Address Register

0x9C000B2C

G22.11

Spi_status_2

SPI Status2 Register

0x9C000B30

G22.12

Spi_err_status

SPI Error Status

0x9C000B34

G22.13

Mem_data_addr

Memory Data Address

0x9C000B38

G22.14

Mem_parity_addr

Memory Parity Address

For SPI_NOR is reserved.

0x9C000B3C

G22.15

Spi_col_addr

SPI Column Page Address

For SPI_NOR is reserved.

0x9C000B40

G22.16

Spi_bch

SPI BCH Configuration Register

For SPI_NOR is reserved.

0x9C000B44

G22.17

Spi_intr_msk

SPI Interrupt Mask Register

0x9C000B48

G22.18

Spi_intr_sts

SPI Interrupt Status Register

0x9C000B4C

G22.19

Spi_page_size

SPI Device Page Size

Address

Group No.

Register Name

Register Description

0x9C000B80

G23.0

Spi_protect_cfg

Protect Configuration Register

0x9C000B84

G23.1

Spi_region0_start_addr

Protection Region0 Start Address

0x9C000B88

G23.2

Spi_region0_size

Size of Protection Region0

0x9C000B8C

G23.3

Spi_region1_start_addr

Protect Region1 Start Address

0x9C000B90

G23.4

Spi_region1_size

Size of Protection Region1

0x9C000B94

G23.5

Spi_region2_start_addr

Protect Region2 Start Address

0x9C000B98

G23.6

Spi_region2_size

Size of Protection Region2

0x9C000B9C

G23.7

Spi_scramble1

SPI Scramble1 Register

0x9C000BA0

G23.8

Spi_scramble2

SPI Scramble2 Register

0x9C000BA4

G23.9

Spi_scramble3

SPI Scramble3 Register

17.5.2 Registers Description

RGST Table Group 22SPI Controller Registers

22.0 SPI Control Register (spi ctrl)
Address: 0x9C000B00
Reset: 0x0117 0003


Field NameBitAccessDescription
SPI BUSY31ROSPI controller busy
0: SPI DEVICE is in IDLE state
1: SPI DEVICE is in busy
Reserved30RODefault to be zero
PAGE ACCESS29RWPage access mode
0: SPI CS B raise when each read command end
1: SPI CS B keep in page mode when read command end and read command is identified (OCP bus read or auto identify customized read command)
AUTO MODE28RW

Auto to page program and page read
1'b1: Enable auto mode
1'b0: Disable auto mode

Auto mode: CPU will enable controller once to finish a page program or a page read operation.

AUTO CMD EN27RW

Auto Command Enable
When use Auto mode, user can define the PRGM EXE cmd or READ TO CACHE cmd in regis- ter(SPI CTRL.MULTI CMD).
1'b1: use define cmd MULTI CMD

1'b0:usedefault cmd(PRGM EXE:10h, READ TO CACHE: 13h)

AUTO 4BYTE ADDR EN

26

RW

Auto do opearation with 4 bytes addr mode
1'b0: 4bytes addr mode is not auto enabled.
1'b1: 4bytes addr mode is auto enabled. default is 1'b0.

FLASH B SEL

25

RW

Select SPI FLASH Chip B
0: chip B unselected 1: chip B selected

FLASH A SEL

24

RW

Select SPI FLASH Chip A
0: chip A unselected 1: chip A selected

USEABLE DQ

23:20

RW

Useable Serial Interface data bits
Bit 4: DQ0 data pin Bit 5: DQ1 data pin Bit 6: DQ2 data pin Bit 7: DQ3 data pin
Auto-configure bit mode by this register.(referring to auto- configure table)

AUTO SPI WEL EN

19

RW

Auto write enable latch
0: SPI write enable is not auto enabled
1: SPI write enable is auto enabled
This bit only affect OCP bus write command and auto identify customized write command

SCK MODE

18:16

RW

SPI clock frequency division selection
1: CLK SPI/2
2: CLK SPI/4
3: CLK SPI/6
4: CLK SPI/8
5: CLK SPI/16
6: CLK SPI/24
7: CLK SPI/32
Default is 7(32 division) Note:
Don't Support SPI CLK = CLK SPI.

MULTI CMD15:8RWMulti command for auto mode cmd or customer cmd to be send to SPI DEVICE
Function 1:used for auto mode, user can define
PRGM EXE or READ TO CACHE cmd. Function 2: used to define customer command.

SPI NAND EN

7

RW

SPI NAND enable signal
1'b1: Indicate it is SPI NAND controller.
1'b0: Indicate it is SPI NOR controller.

CUSTOMER DATA LEN SRC

6:4

RW

Byte length for SPI data
0: no need to transfer data
1: 1 byte
2: 2 bytes
3: 3 bytes
4: 4 bytes

Reserved

3

RO

Default to be zero


CUSTOMER WRITE SRC


2


RW


Read from or write to flash
0: to read from flash
1: to write to flash

CUST ADDR LEN

1:0

RW

Byte length for SPI address
0: no need to transfer address
1: 1 byte
2: 2 bytes
3: 3 bytes



22.1 SPI Timing Register (spi timing)
Address: 0x9C000B04
Reset: 0x012A 0000



Field NameBitAccessDescription
Reserved31:27RODefault to be zero
CS SH CYC26:22RW

SPI CS B setup cycles and hold cycles
Cycles for SPI CS B setup/hold, setting value =
10(ns)*CLK SPI(?MHZ)/1000.

For example, when CLK SPI=400MHZ, the setting value =
10*400/1000 = 4.
Note:10(ns) is SPI FLASH device's real max SPI CS B
setup/hold timing.

CS DISACTIVE CYC

21:16

RW

SPI CS B disactive cycles
Cycles to separate two SPI CS B, the unit is CLK SPI. setting value = 105(ns)*CLK SPI(?MHZ)/1000.
For example, when CLK SPI=400MHZ, the setting value =
105*400/1000 = 42.
Note:105(ns) is SPI FLASH device's real max disactive tim- ing.

Reserved

15:4

RO

Default to be zero


READ TIMING SEL


3:1


RW


Sample read data timing option
0: normal timing (falling edge of SPI CLK)
1: delay 1 CLK SPI cycle from falling edge of SPI CLK to sample data.
2: delay 2 CLK SPI cycle from falling edge of SPI CLK to sample data.
3: delay 3 CLK SPI cycle from falling edge of SPI CLK to sample data.
4: delay 4 CLK SPI cycle from falling edge of SPI CLK to sample data.
5: delay 5 CLK SPI cycle from falling edge of SPI CLK to sample data.
6: delay 6 CLK SPI cycle from falling edge of SPI CLK to sample data.
7: delay 7 CLK SPI cycle from falling edge of SPI CLK to sample data.

WRITE TIMING SEL

0

RW

SPI CLK output timing option
0: normal timing
1: advance one system clock cycle to send data



22.2 SPI Page Address Regsister (spi page addr)
Address: 0x9C000B08
Reset: 0x0


Field NameBitAccessDescription
PAGE ADDR BYTE331:24RWPage Address[31:24] to be send to SPI DEVICE
PAGE ADDR BYTE223:16RWPage Address[23:16] to be send to SPI DEVICE
PAGE ADDR BYTE115:8RWPage Address[15:8] to be send to SPI DEVICE
PAGE ADDR BYTE07:0RWPage Address[7:0] to be send to SPI DEVICE



22.3 SPI Data Register (spi data)

Address: 0x9C000B0C 

Reset: 0x0


Field Name

Bit

Access

Description

DATA BYTE331:24RWDATA[31:24] to be write to or read from SPI DEVICE
DATA BYTE223:16RWDATA[23:16] to be write to or read from SPI DEVICE
DATA BYTE115:8RWDATA[15:8] to be write to or read from SPI DEVICE
DATA BYTE07:0RWDATA[7:0] to be write to or read from SPI DEVICE



22.4 SPI Status Register (spi status)
Address: 0x9C000B10
Reset: 0x0000


Field NameBitAccessDescription
Reserved31:21RO
PRE FETCH BUSY20ROIndicate pre-fetch operation ongoing
SP2 FLAG CHIP B19ROIndicate SP2 mode of chip B
SP2 FLAG CHIP A18ROIndicate SP2 mode of chip A
ADDR 4BYTE FLAG CHIP B17ROIndicate 4bytes address mode status of chip B
1: current ADDR mode is 4 bytes;
0: ADDR mode is normal mode.
This bit will be set to 1'b1 after EN4B command received,
1'b0 after EX4B command received.

ADDR 4BYTE FLAG CHIP A

16

RO

Indicate 4bytes address mode status of chip A




1: current ADDR mode is 4 bytes;




0: ADDR mode is normal mode.




This bit will be set to 1'b1 after EN4B command received,



Reserved



15:8



RO

1'b0 after EX4B command received.

Default to be zero


FLASH STATUS


7:0


RO


Status feed back from SPI DEVICE



22.5SPI Configuration1 Register (spi auto cfg)
Address:0x9C000B14
Reset:0x3B00


Field NameBitAccessDescription
READ FROM CACHE31:24RWRead from cache command
When use the auto mode or DMA function, user can set
READ FROM CACHE command.
CONTINUE MODE23RWWinbond Read continue Mode Enable
1'b0: Disable read continue mode.
1'b1: Enable read continue mode.
PRE FETCH EN22RWPre-fetch enable
0: disable pre-fetch function
1: enable pre-fetch fucntion
This bit afffect OCP/CUST read command
REG SPI EN21Othercustomer command enable/disable
0: customer command has been finished or customer com- mand is not enabled
1: customer command is enabled and triggered
Note: User can not set this bit to disable if it is ever setted to enable. It will go to disable after the current executing command is finished.
AUTO RD CMD EN20RWUser defined READ FROM CACHE command enable
0: use default READ FROM CACHE read command
1: use user defined command.

CHECK DEVICE OIP

19

RW

Check whether device is busy or not
The configureation of GET FEATURE command will be set automatically.
Note: It's convenient to check device's OIP-bit using this configuration. Hardware will check the OIP-bit by send- ing one command and keep reading the OIP-bit.
The entire transmission will be finished after the OIP-bit is low.

AUTO RDSR EN

18

RW

Auto read status register enable
0: SPI read status is not auto enabled
1: SPI read status is auto enabled

DMA OWNER

17

RW

DMA Owner bit
Indicate whether the register is latched by HW.
1'b0: SW can modify the registers.
1'b1: HW has not latch the registers. Note:
the bit only can be set 1 by SW and set 0 by HW.

DUMMY OUT

16

RW

Data in/out selection in dummy cycles
0: SPI DQ will change to input mode in the dummy cycles
1: SPI DQ will change to output mode in the dummy cy- cles

PRGM LOAD

15:8

RW

Page Program Load data command
When use the auto mode or DMA function, user can set
PRGM LOAD command.

Reserved

7:3

RO

Default to be zero


AUTO WREN 2


2


RW


Auto WREN before program execute
When enable this bit, the WREN command will issue before Program Execute command automatically during auto write or dma write operation.

AUTO WREN 1

1

RW

Auto WREN before program load
When enable this bit, the WREN command will issue be- fore Program Load command automatically during auto write or dma write operation.

AUTO WR CMD EN

0

RW

User defined PRGM LOAD command enable
0: use default PRGM LOAD commnad
1: use user defined command.



22.6 SPI Configuration0 Register (spi cfg0)
Address: 0x9C000B18
Reset: 0x8 0004


Field NameBitAccessDescription
ENHANCE DATA31:24RWEnhance data to be send
ENDIAN MODE23RWEndian mode select for OCP
0: Big endian
1: Little endian
DQ BIT SWITCH22RWSwitch serial data pin DQ0 and DQ1
0: DQ1 is high bit and DQ0 is low bit when transferred mode equal to 2
1: DQ0 is high bit and DQ1 is low bit when transferred mode equal to 2
BUF DATA NUM SEL21RWBuffer Data Number Select
1'b1: When receive 32Bytes data into buffer
1'b0: When receive 64Bytes data into buffer
There will issue a interrupt after reading the amount of data. But SPI NAND won't stop after interrupt.
DATA64 EN20RW64-byte customized read/write operation enable
1'b0: use SPI DATA.
1'b1: use SPI DATA64.
SPI TRS MODE19RWTransferring mode for auto WREN and RDSR
0: using SPI CFG4,5,6,7 setting
1: SPI mode transferred
ENHANCE 8BITS SEL18RWEnhance Bits to be transferred
0: 4 bits to be transferred(SPI CFG3[15:12])
1: 8 bits to be transferred
SCK IDLE17RWSPI CLK mode
0: SPI CLK high active at idle state
1: SPI CLK low active at idle state
Reserved16RODefault to be zero
DATA LEN15:0OtherByte length for SPI data
Indicate the number of data will be programmed to flash or read from flash no matter under normal/auto mode or DMA mode.


 
22.7 SPI Configuration1 Register (spi cfg1)
Address: 0x9C000B1C

Reset: 0x0015 0095


Field NameBitAccessDescription
Reserved31:30RODefault to be zero
CUST DUMMY CYC29:24RWSerial interface dummy cycle
The range is from 0 to 63. e
CUST ENHANCE BIT23:22RWSerial interface enhance data mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode
CUST DATA BIT21:20RWSerial interface data mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode
CUST ADDR BIT19:18RWSerial interface address mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode
CUST CMD BIT17:16RWSerial interface command mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode
Reserved15:8RODefault to be zero
CUST DATA DQ IEN7:6RWCustomized DATA bit input enable, only affect 1bit mode
0: input disable
1: DQ0 input enable
2: DQ1 input enable

CUST DATA DQ OEN

5:4

RW

Customized DATA bit output enable, only affect 1bit mode
0: output disable
1: DQ0 output enable
2: DQ0, DQ1 output enable
3: DQ0, DQ1, DQ2 and DQ3 output enable

CUST ADDR DQ OEN

3:2

RW

Customized ADDR bit output enable, only affect 1bit mode
0: output disable
1: DQ0 output enable
2: DQ0, DQ1 output enable
3: DQ0, DQ1, DQ2 and DQ3 output enable

CUST CMD DQ OEN

1:0

RW

Customized CMD bit output enable, only affect 1bit mode
0: output disable
1: DQ0 output enable
2: DQ0, DQ1 output enable
3: DQ0, DQ1, DQ2 and DQ3 output enable



22.8 SPI Configuration2 Register (spi cfg2)
Address: 0x9C000B20
Reset: 0x0015 0095


Field NameBitAccessDescription
Reserved31:30RODefault to be zero
DMA DUMMY CYC29:24RWSerial interface dummy cycle
The range is from 0 to 63. e
DMA ENHANCE BIT23:22RWSerial interface enhance data mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode
DMA DATA BIT21:20RWSerial interface data mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode

DMA ADDR BIT

19:18

RW

Serial interface address mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode

DMA CMD BIT

17:16

RW

Serial interface command mode
0: no need transferred
1: 1 bit mode
2: 2 bit mode
3: 4 bit mode

Reserved

15:8

RO

Default to be zero


DMA DATA DQ IEN


7:6


RW


Customized DATA bit input enable, only affect 1bit mode
0: input disable
1: DQ0 input enable
2: DQ1 input enable

DMA DATA DQ OEN

5:4

RW

Customized DATA bit output enable, only affect 1bit mode
0: output disable
1: DQ0 output enable
2: DQ0, DQ1 output enable
3: DQ0, DQ1, DQ2 and DQ3 output enable

DMA ADDR DQ OEN

3:2

RW

Customized ADDR bit output enable, only affect 1bit mode
0: output disable
1: DQ0 output enable
2: DQ0, DQ1 output enable
3: DQ0, DQ1, DQ2 and DQ3 output enable

DMA CMD DQ OEN

1:0

RW

Customized CMD bit output enable, only affect 1bit mode
0: output disable
1: DQ0 output enable
2: DQ0, DQ1 output enable
3: DQ0, DQ1, DQ2 and DQ3 output enable



22.9 SPI Data Buffer Regsiter (spi data 64)
Address: 0x9C000B24
Reset: 0x0000


Field NameBitAccessDescription
DATA64 BYTE331:24RW

data[31:24] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE,

repeated write this register achieve write data to data buffer when any time

DATA64 BYTE223:16RW

data[23:16] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE,

repeated write this register achieve write data to data buffer when any time

DATA64 BYTE115:8RW

data[15:8] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE,

repeated write this register achieve write data to data buffer when any time

DATA64 BYTE07:0RW

data[7:0] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE,

repeated write this register achieve write data to data buffer when any time




22.10SPI Buffer Address Register (spi buf addr)
Address:0x9C000B28
Reset:0x0000



Field NameBitAccessDescription
Reserved31:22RODefault to be zero
BUF RADDR21:16RW

SPI DATA64 read address
BUF RADDR will decrease by 2 when a read of SPI DATA64 and reading from SPI DEVICE is on going.

User can define the start read address of data buffer by setting BUF RADDR.

Reserved15:6RODefault to be zero
BUF WADDR

5:0

RW

SPI DATA64 write address

BUF WADDR will increase by 2 when every writing of SPI DATA64.

User can define the start write address of data buffer by setting BUF WADDR.



22.11 SPI Status2 Register (spi status 2)
Address: 0x9C000B2C

Reset: 0x2000


Field NameBitAccessDescription
Reserved31:23RODefault to be zero
DMA SUB ST22:20RODMA sub state
0x0: AXI IDLE
0x1: AXI WR INFO
0x2: AXI WR DATA
0x3: AXI RD INFO
0x4: AXI RD DATA
DMA MAIN ST19:18RODMA main state
0x0: DMA IDLE
0x1: DMA DATA
0x2: DMA PARITY
BCH ST17:16RODMA main state
0x0: IDLE
0x1: ENCODE
0x2: DECODE
SPI SRAM ST15:13ROStatus of SRAM
[0]: SRAM conflict, both OCP and customzied read/write
at the same time [1]: SRAM empty [2]: SRAM full

SPI CON ST

12:8

RU

Status of block SPI CON
0: Reset flash, Write Disable (04h)
1: Reset flash, reset winbond Quad mode (FFh)
2: Reset flash, reset winbond Dual mode (FFFFh)
3: Command IDLE
4: Read command executing
5: Page access mode reading
6: Write command executing
7: Write enable(WREN) executing
8: Erase executing
9: Read status register(RDSR) executing
10: Enter 4byte address mode executing
11: Exit 4byte address mode executing
12: exit EON SP2 mode executing
13: Temp state for SP2 mode and 4byte address mode change

SPI OUT ST

7:4

RU

Status of block SPI OUT
0: IDLE state
1: SPI CS B go to low and SPI SCK is not active (Setup time)
2: Transmit command to SPI interface
3: Transmit address to SPI interface
4: Transmit enhance data to SPI interface
5: Count dummy cycle
6: Transmit data to SPI interface
7: SPI CS B keep at low and SPI SCK is not active
8: SPI CS B is going to high and SPI SCK is not acitve
9: SPI CS B go to high and begin counting SPI CS B disac- tive cycles

SPI AXIS ST

3:0

RO

Status of block SPI AXIS
0: IDLE state
1: Send command to SPI CON
2: Request data from SPI CON
3: Send data left in inner 32x8 buffers to OCP BUS



22.12 SPI Controller Error Status Register (spi err status)
Address: 0x9C000B30
Reset: 0x0000


Field NameBitAccessDescription

Field NameBitAccessDescription
Reserved15:3RO

TWO CHIP SEL ERR

2

W1C

Error flag about two chip selected

NO CHIP SEL ERR

1

W1C

Error flag about no chip selected

CUS DATA64 OVERFLOW ERR 

0

W1C

Error flag about DATA64 write data overflow to inner
SRAM(64X8).
For data64 access with the order about write data first, then send write command, the SRAM may hanpen over- flow.
At this time, the error flag will be triggered to indicate overflow status.



22.13 Memory Data Address (mem data addr)
Address: 0x9C000B34
Reset: 0x0000


Field NameBitAccessDescription
MEM DATA ADDR31:0RWMemory Data Address
DMA data start address



22.14 Memory Data Address (mem parity addr)
Address: 0x9C000B38
Reset: 0x0000


Field NameBitAccessDescription
MEM PARITY ADDR31:0RWMemory Parity Address
DMA parity data start address



22.15 SPI Column Page Address (spi col addr)
Address: 0x9C000B3C

Reset: 0x0000


Field NameBitAccessDescription

Reserved

31:16

RO

Default to be zero


COL ADDR BYTE1


15:8


RW


SPI Column Addr
Column Address[15:8] to be send to SPI device

COL ADDR BYTE0

7:0

RW

SPI Column Addr
Column Address[7:0] to be send to SPI device



22.16 SPI BCH configuration Register (spi bch)
Address: 0x9C000B40
Reset: 0x0000


Field NameBitAccessDescription
Reserved31:16RODefault to be zero
BCH DATA LEN15:8RWBCH data length per sector
For bch data:
0x0: 0Byte parity data per BCH sector
0x1: 1Byte parity data per BCH sector
...
0xff: 255Byte parity data per BCH sector
Reserved7RODefault to be zero
BCH DATA MODE6RWBCH data mdoe select
0: 512Byte per BCH.
1: 1k Byte per BCH.
BCH ACC5RW32Byte or 16Byte align
0: 32Byte align.
1: 16Byte align.
AUTO BCH EN4RWAuto BCH function enable
Write 1 enable.
It will encode data before the page program or decode data during page read.
SECTOR NUM3:0RWSet the number N of block
for BCH N= 0˜15(1˜16 blocks)



22.17 SPI Interrupt Mask Register (spi intr msk)

Address: 0x9C000B44
Reset: 0x0000


Field Name

Bit

Access

Description


Reserved

31:3

RO

Default to be zero



PIO DONE MASK


2


RW


PIO done mask
High active. it is used to mask the pio done interrupt.


DMA DONE MASK

1

RW

DMA done mask
High active. it is used to mask the dma done interrupt.


BUF DATA ENOU MASK

0

RW

Buffer data enough mask
High active. it is used to mask the buffer data enough in- terrupt.




22.18 SPI Interrupt Status Register (spi intr sts)

Address: 0x9C000B48
Reset: 0x0000


Field Name

Bit

Access

Description


Reserved

31:3

RO

Default to be zero



PIO DONE INTR


2


RW


PIO done interrupt
When PIO mode transfer finished, it will be high. SW
write 1 to clean this bit.


DMA DONE INTR

1

RW

DMA done interrput
The current dma operation is done. SW write 1 to clear this bit.


BUF DATA ENOU INTR

0

RW

Buffer data enough interrupt
The number of data received from flash has reached the setting amount. The amount is set in spi cfg0[21].
SW write 1 to clear this bit.




22.19 SPI device page size (spi page size)
Address: 0x9C000B4C

Reset: 0x0000



Field NameBitAccessDescription
Reserved31:16RODefault to be zero
ECC EN15RWDevice ECC enable
0x1: Device enable ECC, the data can not be stored in spare space.
0x0: Device disable ECC, the data can be stored in spare space.
SPARE SIZE LEN14:4RWDevice Spare Space length
0x0: 0Byte
0x1: 1Byte
...
0x7ff: 2047Byte
Note:
When SPI NAND, it is spare space in device; when
SPI NOR, it is per page size in device
Reserved3RODefault to be zero
PAGE SIZE LEN2:0RWPage number select
Used for auto mode and DMA mode to count the page number.
For 0˜7, indicate 1˜8k Byte data per page. Example:
1. ECC enable: the page size only decide by PAGE SIZE LEN, if PAGE SIZE LEN = 0x1, it indicates 2k Byte per page.
2. ECC disable: if PAGE SIZE LEN=0x1, and the SPARE SIZE LEN = 64Byte, it indicate (2K + 64)Byte per page.




Group 23SPI Protection/Scramble/Descramble Registers

23.0 Protect Configration Register (spi protect cfg)
Address: 0x9C000B80
Reset: 0x0000


Field NameBitAccessDescription
RSV31:25ROReserved
ignore block erase24RW

Ignore Block Erase Command
This bit can only be written to 1. Write 0 has no effect.
0: normal. Block erase command is not ignored by the
H/W.
1: Ignore the block erase.
For SPI flash that supports the sector-erase com- mand('h20),

this bit must be set to 1 to avoid the protection region is erased by block-erase in protection mode.

Else it should be set to 0.

RSV23ROReserved
wp2 en22RWWrite Protect Enable for Region2
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash can normally be written for pro- tection region2 address.
1: write protection. Address in the protection region2 can not be written.
wp1 en21RWWrite Protect Enable for Region1
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash can normally be written for pro- tection region1 address.
1: write protection. Address in the protection region1 can not be written.
wp0 en20RWWrite Protect Enable for Region0
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash can normally be written for pro- tection region0 address.
1: write protection. Address in the protection region0 can not be written.
RSV19ROReserved

rp2 en

18

RUW

Read Protect Enable for Region2
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash controller obtains the real values stored in the external SPI flash memory.
1: read protection. The SPI flash controller returns a ran- dom value(for CBUS) or a constant 0(for RGST)(for CBUS) or a constant 0(for RGST) for protection region 2

rp1 en

17

RUW

Read Protect Enable for Region1
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash controller obtains the real values stored in the external SPI flash memory.
1: read protection. The SPI flash controller returns a ran- dom value(for CBUS) or a constant 0(for RGST) for protec- tion region 1

rp0 en

16

RUW

Read Protect Enable for Region0
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash controller obtains the real values stored in the external SPI flash memory.
1: read protection. The SPI flash controller returns a ran- dom value(for CBUS) or a constant 0(for RGST) for protec- tion region 0

RSV

15:7

RO

Reserved

flash size

6:4

RUW

SPI Flash Size

This field can be normally accessed only when write this field has no effect and read this field return
{[0],[2],[1]}.

000: 1M Byte flash memory size.

001: 2M Byte flash memory size

010: 4M Byte flash memory size.

011: 8M Byte flash memory size.

100: 16M Byte flash memory size.

101: 32M Byte flash memory size.

RSV3:2ROReserved

out range wp en

1

RUW

Out of Range Write Protect Enable
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash can normally be written for out- of-range(address is equal or larger than the SPI flash size) address.
1: write protection. Out-of-range write will be ignored by the H/W.

out range rp en

0

RUW

Out of Range Read Protect Enable
This bit can only be written to 1. Write 0 has no effect.
0: normal. The SPI flash controller obtains the real values stored in the external SPI flash memory.
1: read protection. The SPI flash controller returns a ran- dom value(for CBUS) or a constant 0(for RGST) for out of range(address is equal or larger than the SPI flash size) read



23.1 Protection Region0 Start Address (spi region0 start addr)
Address: 0x9C000B84
Reset: 0x0000


Field NameBitAccessDescription

region0 start addr high

31:16

 RUW

Protection Region0 Start Address[31:16]




This field can be normally accessed only when rp0 en and




wp0 en are all 0. That is, when rp0 en or wp0 en is 1,




write this field has no effect and read this field returns




{[18:16],[25:22],[31:26],[21:19]}.

region0 start addr low

15:0

 RUW

Protection Region0 Start Address[15:0]




This field can be normally accessed only when rp0 en and




wp0 en are all 0. That is, when rp0 en or wp0 en is 1,




write this field has no effect and read this field returns




{[2:0],[9:6],[15:10],[5:3]}.
For the flash that does not support the sector-erase com-




mand('h20), this start address should be aligned the block




size.Else it should be aligned to sector size.The same rule should be applied to spi region1 start addr and spi region2 start addr. 



23.2 Size of Protection Region0 (spi region0 size)
Address: 0x9C000B88
Reset: 0x0000

Field Name

Bit

Access

Description

RSV

31:16

RO

Reserved

region0 size

15:0

RW

Size of Protection Region0




This field can be normally accessed only rp0 en and




wp0 en are all 0. That is, when rp0 en or wp0 en is 1,




write this field has no effect and read this field returns




{[2:0],[9:6],[15:10],[5:3]}. It can be 0 till 0xffff. The value
0 means 1 byte length and 0xffff means 64k bytes.




For the flash that does not support the sector-erase com-




mand('h20), (region0 size+1) should be multiple of the




block size.Else it should be multiple of the sector size.




The same rule should be applied to spi region1 size and




spi region2 size.



23.3 Protection Region1 Start Address (spi region1 start addr)
Address: 0x9C000B8C

Reset: 0x0000

Field Name

Bit

Access

Description

region1 start addr high

31:16

RW

Protection Region0 Start Address[31:16]




This field can be normally accessed only when rp1 en and




wp1 en are all 0. That is, when rp1 en or wp1 en is 1,




write this field has no effect and read this field returns




{[18:16],[25:22],[31:26],[21:19]}. And the address can be any byte address.

region1 start addr low

15:0

RW

Protection Region0 Start Address[15:0]




This field can be normally accessed only when rp1 en




and wp1 en are all 0. That is, when rp1 en or wp1 en




is 1, write this field has no effect and read this field re-




turns {[2:0],[9:6],[15:10],[5:3]}. And the address should be aligned the sector size.



23.4 Size of Protection Region1 (spi region1 size)
Address: 0x9C000B90
Reset: 0x0000


Field NameBitAccessDescription
RSV31:16ROReserved
region1 size15:0RW

Size of Protection Region0
This field can be normally accessed only rp1 en and wp1 en are all 0. That is, when rp1 en or wp1 en is 1,

write this field has no effect and read this field returns
{[2:0],[9:6],[15:10],[5:3]}. It can be 0 till 0xffff. The value
0 means 1 byte length and 0xffff means 64k bytes. And
(region1 size+1) should be multiple of the sector size



23.5 Lower16bitsofProtectionRegion2StartAddress
(spi region2 start addr low)
Address: 0x9C000B94
Reset: 0x0000

Field Name

BitAccess

Description

region2 start addr high

31:16 RUW

Protection Region0 Start Address[31:16]



This field can be normally accessed only when rp2 en and



wp2 en are all 0. That is, when rp2 en or wp2 en is 1,



write this field has no effect and read this field returns



{[18:16],[25:22],[31:26],[21:19]}. And the address can be any byte address.

region2 start addr low

15:0 RUW

Protection Region0 Start Address[15:0]



This field can be normally accessed only when rp2 en



and wp2 en are all 0. That is, when rp2 en or wp2 en



is 1, write this field has no effect and read this field re-



turns {[2:0],[9:6],[15:10],[5:3]}. And the address should be aligned the sector size.


23.6 Size of Protection Region2 (spi region2 size)
Address: 0x9C000B98
Reset: 0x0000

Field Name

Bit

Access

Description

RSV

31:16

RO

Reserved

region2 size

15:0

 RW

Size of Protection Region0




This field can be normally accessed only rp2 en and




wp2 en are all 0. That is, when rp2 en or wp2 en is 1,




write this field has no effect and read this field returns




{[2:0],[9:6],[15:10],[5:3]}. It can be 0 till 0xffff. The value
0 means 1 byte length and 0xffff means 64k bytes. And




(region2 size+1) should be multiple of the sector size



23.7 SPI Scramble1 Register (spi scramble1)
Address: 0x9C000B9C

Reset: 0x0000


Field NameBitAccessDescription
Reserved15:8RODefault to be zero
DATA TOG7:0RWData toggle out



23.8 SPI Scramble2 Register (spi scramble2)
Address: 0x9C000BA0
Reset: 0x0000


Field NameBitAccessDescription
Reserved15:8RODefault to be zero
ADDR MASK7:0RWAddress mask for data scramble



23.9 SPI Scramble3 Register (spi scramble3)
Address: 0x9C000BA4
Reset: 0x0000


Field NameBitAccessDescription
Reserved15:3RODefault to be zero
DATA POR2:0RWData scramble position rotation