Case download:
riscv.zip
1 Design Brief
In 2010, the RISC-V architecture was born at the University of California, Berkeley. With its streamlined and efficient advantages, it quickly gained the support of academia. After nearly ten years of development, the RISC-V architecture has been widely recognized by academia and industry. With the increasing maturity of the RISC-V ecosystem, future RISC-V-based processors will be widely used.
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PicoRV32 supports 32-bit AXI4-Lite master bus system, our SP7021 SOC platform is 64-bit AXI bus system, so we provide riscv_wrap.v module to achieve 32bit to 64bit conversion; as shown below:
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we choose axi_ bus_ s32_bridge module from Bus Bridge series, it provides AXI slave bus interface to connect our IP,as shown in the figure below:
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In this experiment, the related experiment is completed with the FPGA daughter board supporting the Plus1 SP 7021 practice platform. The development tool of the FPGA daughter board uses XILINX's Vivado integrated development environment (version number 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system Verification, this experiment provides the corresponding design reference basic files, as follows
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