Open source RISC-V CPU core design practice

Case download:

1 Design Brief

In 2010, the RISC-V architecture was born at the University of California, Berkeley. With its streamlined and efficient advantages, it quickly gained the support of academia. After nearly ten years of development, the RISC-V architecture has been widely recognized by academia and industry. With the increasing maturity of the RISC-V ecosystem, future RISC-V-based processors will be widely used.

PicoRV32 is an open source RISC-V processor core that implements the RISC-V RV32IMC instruction set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally includes a built-in interrupt controller, implemented in Verilog hardware description language, which can be obtained from the RISC-V website http://riscv.org/ code, tools (gcc, binutils, etc.). PicoRV32 uses RISC-V ISR, but Trap / interrupt / interrupt return is redesigned, using a simplified scheme to complete the interrupt operation and implement a simple built-in custom interrupt controller.

The focus of this PicoRV32 is to pursue the optimization of area and frequency. The cost of its published data on Xilinx7-Series FPGA is 750-2000 LUTs, and it can be integrated to the main frequency of 250-450MHz. This practice deeply integrates the theoretical knowledge of computer architecture with the engineering practice of SP7021 + FPGA SOC platform to realize CPU-related functions, and strives to enable students to quickly and deeply master the design capabilities of embedded CPU cores for future large-scale SoC design and high-performance core Design lays a solid foundation

2 Design specifications

1  Supportt AMBA4 AXI 32 bit Bus interface.

2  Support RISC-V RV32IMC Instruction Set

3 Support Extend Co-Processor Interface

3 SOC integration

3.1 Implementation of hardware platform for RISC-V CPU experiment project

PicoRV32 supports 32-bit AXI4-Lite master bus system, we choose axi_ bus_ s32_bridge module from Bus Bridge series, it provides AXI slave bus interface to connect our IP,as shown in the figure below:

Open

In this experiment, the related experiment is completed with the FPGA daughter board supporting the SP 7021 practice platform. The development tool of the FPGA daughter board uses XILINX's Vivado integrated development environment (version number 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system Verification, this experiment provides the corresponding design reference basic files, as follows

Open

The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the motherboard is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the motherboard and the FPGA

3.2 Implementation of System Software Platform of RISC-V CPU Experiment Project

The supporting CPU system compilation and development tools have been integrated into the IDE development tools.

RISC-V CPU IP design practice preparation work:

In the IDE environment, as shown below, select the sp7021 project name, click the right mouse button and select Copy in the pop-up menu

Next, select the sp7021 project name again

Click the right mouse button and select Paste in the pop-up menu, the following picture appears

Fill in riscv in the Project name box to complete the creation of riscv project name and directory, as shown below

Next, you need to copy all the files and folders under the installation directory \SP7021\example\riscv to the gpio project directory built above (the path is: installation directory \SP7021\workspace\riscv\), the file with the same name is selected to be overwritten, so RISC-V Program codes and compilers required for CPU IP design practice are placed in the following paths:

1）In the install directory \SP7021\workspace\riscv\picorv32\firmware\hello.c

2）In the install directory \SP7021\workspace\riscv\riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-w64-mingw32 folder is the RISC-V compiler

3）In the install directory \SP7021\workspace\riscv\main.c

Finally, as shown in the figure below, select the red box 1 with the mouse, then click the right mouse button to display the drop-down menu, and then select the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment.

hello.c

#include "firmware.h"

void hello(void)

{

    print_str("hello world \n");

    unsigned int i, add=0, mul, div;

    for (i=1;i<=100;i++)

    {

        add = add + i;

        mul = add * i;

        div = mul / i;

        print_str("index");print_str("\t");

        print_str("add value");print_str("\t");

        print_str("mul value");print_str("\t");

        print_str("div value \n");

        print_dec(i); print_str("\t"); print_dec(add); print_str("\t");

        print_str("\t");

        print_dec(mul); print_str("\t"); print_dec(div); print_str("\n");

        print_str("**************************************************** \n");

    }

    print_str("RISCV selftest finished \n");

}

The application program of PicoRV32 CPU realizes the programming of addition, multiplication and division of 32-bit unsigned numbers. In the IDE environment, when the entire project is compiled, hello.c will be automatically compiled by riscv gcc and converted into a binary code file firmware.inc for the main program of the project to call.

main.c

UINT8 fw[] = {

#include "picorv32/firmware/firmware.inc"

};

int main(void)

{

    printf("Build @%s, %s\n", __DATE__, __TIME__);

    /* copy riscv fw to 0x00000000 */

    memcpy(0x00000000, fw, sizeof(fw));

    printf("riscv fw (%08x %08x) size: %d bytes\n", *(UINT32 *)0, *(UINT32 *)4, sizeof(fw));

    hw_init();

    sys_init();

    disp_hdmi_init();

    fbio_init();

    while(1);

}

The main program of the entire project runs on the SP7021 CPU. After power-on, the initialization of the SP7021 + FPAG system is completed, as follows: 1: Initialize the DRAM space, put the PicoRV32 CPU binary code file firmware.inc into DRAM; 2: Reset the FPGA, and point the PicoRV32 CPU Boot address in the FPGA to the DRAM address 0; 3: After resetting the FPGA, the main program enters idle mode, and the PicoRV32 CPU in the FPGA starts to fetch and execute instructions from the DRAM, and the execution result is displayed through the serial port of SP7021

3.3 Run the Program code

After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window